For many fields of application, it is customary and necessary to link a computer with other computers or data stations.
As described, for example, in GDR-WP 208254, this can be achieved through a serial interface. However, this has the disadvantage of taking a great deal of time. Alternatively, the connection can be established through a bus coupling.
Couplings are known between master units on one side of the bus and either slave or master units on the other side. The known technical solutions attempt to expand limited bus systems through their bus parameters (such as bus load, limited bus arbitrage). Because further resources are thus coupled in, the power of the computer systems is increased in this way and/or a better matching of bus or computer systems to the individual technical or engineering application becomes possible. Thus GDR-WP 231672 discloses a technical solution, in which a bus receiver, which is plugged into the system bus of a master cassette and which contains units to establish the status and to activate an extension, is connected via a transmission cable to a bus driver which is plugged into the system bus of the slave cassette and which contains units for accepting the status, for synchronization, and for bus control. The transmission cable contains multiplex lines for data and addresses, interrupt lines, status lines, an extension-activation line, a data enable control line, and a bus access acknowledgment line.
A disadvantage of this technical solution is that it can only establish a coupling between the master cassette on one side and the slave cassette on the other side.
Moreover, a circuit arrangement for coupling system-external microprocessors to a given bus system is also known (GDR-WP 237923). Here, data are exchanged via a two-gate memory through control signals from an interface connected to the given bus system and through an interface connected to the system-external microprocessors. A single circuit delivers acknowledgment signals to the bus systems on request and a command signal to the two-gate memory. The acknowledgment signal for the given bus system serves as a polling signal for a decoder to create interrupts for a particular system-external microprocessor.
The intermediate storage of data is a disadvantage here. This delays data exchange as a whole and restricts the time available for data exchange. Another disadvantage is the effort needed in terms of software to link the coupling arrangement into the overall computer system.
Coupling solutions, where computer units are connected through peripheral processors (German Auslegeschrift 2,924,899), also have these disadvantages: additional interrupts here further impair the time balance.
All the technical solutions share the common disadvantage that either the master units of the system buses to be expanded do not have direct unhindered access to the resources of the units of the respectively remote bus sides or that only the master unit of one bus side can use the resources of the other bus side, but no master unit may be present on the other bus side.